Flip-chip wafer level package and methods thereof

ABSTRACT

An electronic package includes a flip-chip component having a first die coupled to a flip-chip substrate, second die stacked on the first die, an encapsulation compound formed around the first die and the second die, a set of through encapsulant vias (TEVs) providing a set of electrical connections from a first side of the electronic package to a second side of the electronic package through the encapsulation compound to the flip-chip substrate, and a redistribution layer electrically connecting a set of contacts on the second die to the set of TEVs on the first side of the electronic package.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional of U.S. patent application Ser. No.13/731,123 filed Dec. 31, 2012, which is incorporated herein byreference in its entirety.

FIELD OF THE DISCLOSURE

This disclosure relates to devices and methods of manufacturingelectronics, and more particularly, to electronic packages andmanufacturing methods thereof.

BACKGROUND

In manufacturing integrated circuits (ICs), the ICs, called chips ordies, are generally packaged prior to distribution and integration withother electronic assemblies. This packaging usually includesencapsulating the chips in a material and providing electrical contactson the exterior of the package to provide an interface to the chip. Chippackaging, amongst other things, may provide protection fromcontaminants, provide mechanical support, disperse heat, and reducethermo-mechanical stresses.

Because of the relation between IC fabrication and IC packaging, ICpackaging also must generally progress with the rapid advancements inthe semiconductor industry. In particular, there is an ongoing to desireto package ICs and other electronics to make them smaller, faster, andmore reliable.

SUMMARY

In a first aspect of this disclosure, an electronic package includes aflip-chip component having a first die coupled to a flip-chip substrate,second die stacked on the first die, an encapsulation compound formedaround the first die and the second die, a set of through encapsulantvias (TEVs) providing a set of electrical connections from a first sideof the electronic package to a second side of the electronic packagethrough the encapsulation compound to the flip-chip substrate, and aredistribution layer electrically connecting a set of contacts on thesecond die to the set of TEVs on the first side of the electronicpackage.

In another aspect of this disclosure, a method for manufacturing anelectronic package is provided. The method includes providing aflip-chip component having a first die coupled to a flip-chip substrate,adhering the first die to a second die, forming an encapsulationcompound around the first die and the second die, drilling a set ofthrough encapsulant vias (TEVs) from a first side of the electronicpackage to the flip-chip substrate located on a second side of theelectronic package, filling the set of TEVs with an electricallyconductive material, and applying a redistribution layer electricallyconnecting a set of contacts on the second die to the set of TEVs on thefirst side of the electronic package.

In a further aspect of this disclosure, a memory device includes aflip-chip component having a first die coupled to a flip-chip substrate,a second die stacked on the first die, an encapsulation compound formedaround the first die and the second die, a set of through encapsulantvias (TEVs) providing a set of electrical connections from a first sideof the electronic package to a second side of the electronic packagethrough the encapsulation compound to the flip-chip substrate, and aredistribution layer electrically connecting a set of contacts on thesecond die to the set of TEVs on the first side of the electronicpackage. The first die and/or the second die includes a memory function.

In yet another aspect of this disclosure, an electronic package includesa first electronic package, and a second electronic package. The secondelectronic package includes a flip-chip component having a first diecoupled to a flip-chip substrate, a second die stacked on the first die,an encapsulation compound formed around the first die and the seconddie, a set of through encapsulant vias (TEVs) providing a set ofelectrical connections from a first side of the electronic package to asecond side of the electronic package through the encapsulation compoundto the flip-chip substrate, and a redistribution layer electricallyconnecting a set of contacts on the second die to the set of TEVs on thefirst side of the electronic package. The first electronic package isstacked together with the second electronic package to form apackage-on-package (PoP) electronic package.

BRIEF DESCRIPTION OF THE DRAWINGS

To further clarify the above and other advantages and features of thepresent invention, a more particular description of the invention willbe rendered by reference to specific embodiments thereof that areillustrated in the appended drawings. It is appreciated that thesedrawings depict only typical embodiments of the invention and aretherefore not to be considered limiting of its scope. The invention willbe described and explained with additional specificity and detailthrough the use of the accompanying drawings in which:

FIG. 1 is a flip-chip wire-bond package.

FIG. 2 is a flip-chip wafer-level package.

FIG. 3 illustrates a method for manufacturing the flip-chip wafer-levelpackage shown in FIG. 2.

FIGS. 4-13 depict a process flow for manufacturing the flip-chipwafer-level package shown in FIG. 2.

FIGS. 14-23 depict an alternative process flow for manufacturing theflip-chip wafer-level package shown in FIG. 2.

FIG. 24 is a flip-chip wafer-level package with a three chipconfiguration.

DETAILED DESCRIPTION

Reference will now be made to figures wherein like structures will beprovided with like reference designations. It is understood that thedrawings are diagrammatic and schematic representations of exemplaryembodiments of the invention, and are not limiting of the presentinvention nor are they necessarily drawn to scale.

Chips (alternatively referred to herein as dies) are generally packagedprior to distribution and integration with other electronic assemblies.This packaging usually includes encapsulating the chips in a materialand providing electrical contacts on the exterior of the package toprovide an interface to the chip. Chip packaging, amongst other things,may provide protection from contaminants, provide mechanical support,disperse heat, and reduce thermo-mechanical stresses.

Stacking multiple chips within a single chip package is an increasinglycommon packaging requirement in order to reduce, for example, overallassembly size, functional circuit speed, and overall costs.

FIG. 1 is a flip-chip wire-bond package 10. Flip-chip wire-bond package10 includes two chips 1, 3, arranged such that chip 1 is stacked on topof chip 3. Chip 3 is coupled to a layered substrate 11 by way ofbump-underfill layer 9. Layered substrate 11 is in turn coupled tosolder balls 13. In this way, chip 3 is indirectly coupled, bothphysically and electrically, to some of the solder balls 13 such that asubset of solder balls 13 form an electrical interface for chip 3. Chip1 is likewise electrically coupled to the layered substrate 11 by way ofbonded wires 5. In this way, chip 1 is indirectly electrically coupledto some of solder balls 13 such that a subset of solder balls 13 formsan electrical interface for chip 1. Encapsulation compound 7 is moldedaround the chips 1, 3, the wire bonds 5, and the bump-underfill layer 9.Encapsulation compound 7 is generally formed on top of layered substrate11. In this way flip-chip wire-bond package 10 forms a unitary packagewith an interface provided by way of solder balls 13.

While flip-chip wire-bond package 10, and other wire bond packaging,provides a means for package production, ongoing advancements in theindustry have pushed towards lower package profiles and increasedelectrical performance.

Through Silicon Vias (TSVs) provide a connection through thesemiconductor wafer for stacking purposes. TSVs may provide betterelectrical performance and a lower profile. Costs and reliable supplychain management, however, may generally limit widespread TSV usagewithin industry.

FIG. 2 is a flip-chip wafer-level package 10′. Flip-chip wafer-levelpackage 10′ includes a flip-chip component 18 which includes die 3′coupled to flip-chip substrate 11′. As shown, die 3′ is coupled toflip-chip substrate 11′ by way of bump-underfill layer 9′.

Die 1′ is arranged on top of die 3′, and encapsulation compound 7′ isformed around die 1′ and die 3′. Die 1′ may be adhered to die 3 prior toforming encapsulation compound 7′ by applying an adhesive 15 such as adie attach film (DAF) between dies 1′ and 3′. Adhesive 15 may beapplied, for example, through laminating, printing, or dispensing theadhesive onto one of the dies and then placing the remaining die ontothe adhesive prior to curing.

A set of through encapsulant vias (TEVs) 19 provide electricalconnections through the encapsulation compound 7′ of flip-chipwafer-level package 10′. Additionally, a redistribution layer 17electrically connects TEVs 19 to die 1′. Flip-chip wafer-level package10′ further includes solder balls 13′ adhered to the flip-chip substrate11′, and possibly a protection layer 16 covering redistribution layer 17and the TEVs 19 to protect the otherwise exposed components 16′.Flip-chip wafer-level package 10′ may also include a dielectric layerbetween the second die and the redistribution layer.

Dies 1′ and 3′ may be fabricated according to standard semiconductormanufacturing processes. That is, generally after an ingot is grown itis sliced into wafers. Areas of the wafer may undergo deposition,removal, patterning, and doping processes. Once the wafer has beenprocessed, the wafer is generally mounted and diced into individualdies. Die 3′, in particular, is further processed and provided as partof the flip-chip component 18. That is, die 3′ is processed usingflip-chip technology such that die 3′ is coupled to flip-chip substrate11′ thereby forming the flip-chip component 18.

Encapsulation compound 7′ is generally composed of a plastic material,but other materials, such as ceramics and metals and silicon or glass,may be used if desired. Thermosetting molding compounds, in particular,are a type of plastic material based on epoxy resins. These types ofcompounds have historically been used in electronic packagingapplications. Thermoplastics, such as a high purity fluoropolymer, areanother type of plastic materials which may be used as encapsulationcompound 7′.

TEVs 19 are formed by drilling holes through encapsulation compound 7′and then filling the drilled holes with an electrically conductivematerial. The drilling of the TEVs holes may be performed, for example,with a mechanical drill, a laser, or through chemical etching.

Contacts on die 1′ may be arranged in a variety of ways. As depicted inFIG. 2, however, die 1′ is arranged such that its contacts are arrangedopposite of contacts on die 3′. In this way, redistribution layer 17 canbe applied directly over die 1′ and thereby connect to the contacts ondie 1′. Redistribution layer 17 is preferably applied using thin-filmtechnology. Thin-film deposition can be effectuated, for example, viasputtering, plating, or chemical vapor deposition (CVD), amongst othertechniques.

Electronic packages built in accordance with flip-chip wafer-levelpackage 10′ may further include, or be combined with, one or more of thefollowing features. Die 1′ and/or die 3′ may include a memory function.For example, flip-chip wafer-level package 10′ may implement dynamicrandom access memory (DRAM). An electronic package may include a firstelectronic package and a second electronic package, at least one ofwhich is built in accordance with flip-chip wafer-level package 10′; thefirst electronic package may be stacked together with the secondelectronic package to form a package-on-package (PoP) electronicpackage. In this way, dies 1′ and 3′ as depicted in FIG. 1 aresubstituted with the first and second electronic packages, while theremaining structure of flip-chip wafer-level package 10′ remainsrelatively the same.

Flip-chip wafer-level package 10′ may include additional dies stacked ondie 3′ of the flip-chip component 18. That is, flip-chip wafer-levelpackage 10′, in addition to dies 1′ and 3′, may include more dies, suchthat the total number of dies in flip-chip wafer-level package 10′ isthree or more.

Flip-chip wafer-level package 10′ may be constructed such that thedistance between the set of contacts on the second die and a surface ofthe first side of the electronic package is less than about 20 μm. Sucha configuration reduces package size and may reduce overall electronicassembly size.

Further details regarding the manufacturing of wafer-level package 10′are discussed below with reference in particular to FIGS. 3-23. FIG. 3illustrates a method for manufacturing the flip-chip wafer-level packageshown in FIG. 2, while FIGS. 4-13 depict a process flow formanufacturing the flip-chip wafer-level package 10′ shown in FIG. 2, andFIGS. 14-23 depict an alternative process flow for manufacturing theflip-chip wafer-level package 10′ shown in FIG. 2.

Referencing FIG. 3, a method 30 for manufacturing an electronic packageis provided. In FIG. 4, a mold carrier 33 with releasable tape 35 isprovided. For example, an adhesive foil may be used as releasable tape35 and applied thereon to mold carrier 33, e.g. by lamination.

In FIG. 5, die 1′ is adhered to mold carrier 33 by way of releasabletape 35. Preferably, die 1′ is placed face down on releasable tape 35.That is, die 1′ is arranged such that the electrical contacts thereonare directed towards the mold carrier 33. Dies 1′ and 3′ may befabricated according to standard semiconductor manufacturing processes.That is, generally after an ingot is grown it is sliced into wafers.Areas of the wafer may undergo deposition, removal, patterning, anddoping processes. Once the wafer has been processed, the wafer isgenerally mounted and diced into individual dies. Die 3′, in particular,is further processed and provided as part of the flip-chip component 18.That is, die 3′ is processed using flip-chip technology such that die 3′is coupled to flip-chip substrate 11′ thereby forming the flip-chipcomponent 18.

In FIG. 6, adhesive 15 is then applied to a side of die 1′. Preferably,adhesive 15 is applied on the side of die 1′ opposite to the side of die1′ adhered to mold carrier 33′, or put more simply, adhesive 15 ispreferably applied to the back side of die 1′. Die 1′ may be adhered todie 3 by applying an adhesive 15 such as a die attach film (DAF) betweendies 1′ and 3′. Adhesive 15 may be applied, for example, throughlaminating, printing, or dispensing the adhesive.

Method 30 then includes, as shown in FIG. 7, providing 21 a flip-chipcomponent 18 having die 3′ coupled to flip-chip substrate 11′, andadhering 23 die 3′ to die 1′. Since, as discussed above with referenceto FIG. 6, the back side of die 1′ already has adhesive 15 appliedthereto, die 3′ may be adhered to die 1′ by way of the previouslyprovided adhesive 15. In this way, flip-chip component 18 is adhered tomold carrier 33 by the adherence of dies 1′ and 3′. If necessary,adhesive 15 may be cured by the addition of energy. For example,chemical, thermal, or ultraviolet (UV) light may be added to cureadhesive 15.

Method 30 further includes, as shown in FIG. 8, forming 25 encapsulationcompound 37 around dies 1′ and 3′. Encapsulation compound 7′ isgenerally composed of a plastic material, but other materials, such asceramics and metals, may be used if desired. Thermosetting moldingcompounds, in particular, are a type of plastic material based on epoxyresins. These types of compounds have historically been used inelectronic packaging applications. Thermoplastics, such as a high purityfluoropolymer, are another type of plastic materials which may be usedas encapsulation compound 7′. It is noted that an exposed side offlip-chip substrate 11′ may be left uncovered with encapsulationcompound 7′. In order to not cover flip-chip substrate 11′ withencapsulation compound 7′, a top foil in a compression molding tool maybe used or injection molding technology may be employed. Anotherpossibility would be to grind the attached mold compound down to thesubstrate contacts after molding.

In FIG. 9, mold carrier 33 is released after encapsulation compound 37has been formed. As part of releasing mold carrier 33, adhesive 35 mayalso be removed, and a dielectric layer 39 may be applied andstructured. Application of dielectric layer 39 may be performed, forexample, by spin coating and photolithography, or by lamination andlaser structuring. Dielectric layer 39 may also be applied later on, orcan be structured contemporaneously with TEV drilling.

Method 30 further includes drilling 27, as shown in FIG. 10, a set ofthrough encapsulant vias (TEVs) 19 from a first side of the electronicpackage to flip-chip substrate 11′ located on a second side of theelectronic package. TEVs 19 are formed by drilling holes throughencapsulation compound 7′ and possibly the dielectric material, if notpreviously structured, as shown in FIG. 10, and then filling the drilledholes with an electrically conductive material, as shown in FIG. 11. Thedrilling of the TEVs holes may be performed, for example, with amechanical drill, a laser, or through chemical etching. In performingthe drilling, via stops on flip-chip substrate 11′ may be used toprovide a stopping point for the drilling.

Method 30 then includes, as shown in FIG. 11, filling 29 TEVs 19 with anelectrically conductive material, and applying 31 redistribution layer17, thereby electrically connecting a set of contacts on die 1′ to TEVs19 on a first side of the electronic package 10′. Filling 29 the TEVs 19with an electrically conductive material, and applying 31 redistributionlayer 17, may be performed in distinct parts, or may occurcontemporaneously in a single step. Redistribution layer 17 electricallyconnects TEVs 19 with solder ball positions and may also provide on-chipconnections and connections between multiple chips in a given plane.

In FIG. 12, a solder stop or back side protection (BSP) such asprotection layer 16 may be applied on top of redistribution layer 17,thereby giving the electronic package 10′ a consistent black backside,protecting redistribution layer 17, and protecting the TEVs 19, forexample. This solder stop or BSP may be applied using a spin-coating,lamination, spray coating or printing process.

Finally, in FIG. 13, solder balls 13′ are applied or adheared toflip-chip substrate 11′ and the individual packages, if not alreadyseparated, may be separated at this point. Solder balls 13′ may beconventional solder balls, semi-balls, polymer core balls or land gridarrays (LGA), for example, and may be adhered, for instance, viasoldering thereto.

In addition to producing a smaller, more efficient package, flip-chipwafer-level package 10′ allows for separately testing and burning-inflip-chip component 18 between fabrication processes. That is, flip-chipcomponent 18 may be separately fabricated, tested, and burned-in, priorto continuing manufacture of flip-chip wafer-level package 10′ .

Referencing FIGS. 14-23, an alternative process flow is shown. In FIG.14, a mold carrier 33 with releasable tape 35 is provided. That is,releasable tape 35 is applied to mold carrier 33. For example, anadhesive foil may be used as releasable tape 35 and laminated thereon tomold carrier 33.

In FIG. 15, flip-chip component 18 is adhered to mold carrier 33 via thepreviously applied releasable tape 35. More particularly, flip-chipsubstrate 11′ is adhered to mold carrier 33 via releasable tape 35.

Similar to the process flow heretofore described, in FIG. 16, die 1′ isthen attached to die 3′ by way of adhesive 15. Adhesive 15 is applied toa side of die 3′, or alternatively die 1′. Preferably, adhesive 15 isapplied on the side of die 3′ opposite to the side of die 3′ adhered toflip-chip substrate 11′, or put more simply, adhesive 15 is preferablyapplied to the back side of die 3′. Die 1′ may be adhered to die 3′ byapplying an adhesive 15 such as a die attach film (DAF) between dies 1′and 3′. Adhesive 15 may be applied, for example, through laminating,printing, or dispensing the adhesive. Dies 1′ and 3′ are then adheredtogether by way of the previously applied adhesive 15. In this way, die1′ is adhered to mold carrier 33 by the adherence of dies 1′ and 3′. Ifnecessary, adhesive 15 may be cured by the addition of energy. Forexample, chemical, thermal, or ultraviolet (UV) light may be added tocure adhesive 15. Preferably, dies 1′ and 3′ are positioned as shownsuch that the respective contacts are opposite one another.

As shown in FIG. 17, encapsulation compound 7′ is formed on and arounddies 1′ and 3′, and mold carrier 33 is removed along with removableadhesive 35. Encapsulation compound 7′ is generally composed of aplastic material, but other materials, such as ceramics and metals, maybe used if desired. Thermosetting molding compounds, in particular, area type of plastic material based on epoxy resins. These types ofcompounds have historically been used in electronic packagingapplications. Thermoplastics, such as a high purity fluoropolymer, areanother type of plastic materials which may be used as encapsulationcompound 7′.

In FIG. 18, the contacts, or applied posts of die 1′ may then exposedby, for example, grinding encapsulation compound 37 until the posts areexposed and encapsulation compound 7′ forms a substantially plannersurface with the surface of die 1′. Alternatively, the contacts, orapplied posts, may be exposed by laser drilling through encapsulationcompound 7′. As a further option, the side of die 1′ having the contactsmay be left relatively uncovered with encapsulation compound 7′. Inorder to not cover flip-chip substrate 11′ with encapsulation compound7′, a top foil in a compression molding tool may be used or injectionmolding technology may be employed.

In FIG. 19, dielectric layer 39 is applied and at least partlystructured. Application of dielectric layer 39 may be performed, forexample, by spin coating, or by lamination and laser structuring.Dielectric layer 39 may also be applied later on, or can be structuredcontemporaneously with TEV drilling.

In FIG. 20, TEVs 19 are drilled, and in FIG. 21, they filled with anelectrically conductive material. The TEVs 19 proceed from a first sideof the electronic package to flip-chip substrate 11′ located on a secondside of the electronic package. TEVs 19 are formed by drilling holesthrough encapsulation compound 7′ and possibly the dielectric layer 39,and then filling the drilled holes with an electrically conductivematerial. The drilling of the TEVs holes may be performed, for example,with a mechanical drill, a laser, or through chemical etching. Inperforming the drilling, via stops on flip-chip substrate 11′ may beused to provide a stopping point for the drilling.

In FIG. 21, redistribution layer 17 is applied to electrically connectTEVs 19 to die 1′. Filling 29 the TEVs 19 with an electricallyconductive material, and applying 31 redistribution layer 17, may beperformed in distinct parts, or may occur contemporaneously in a singlestep. Redistribution layer 17 electrically connects TEVs 19 with solderball positions and may also provide on-chip connections and connectionsbetween multiple chips in a given plane.

In FIG. 22, a solder stop or back side protection (BSP) such asprotection layer 16 may be applied on top of redistribution layer 17,thereby giving the electronic package 10′ a consistent black backside,protecting redistribution layer 17, and protecting the TEVs 19, forexample. This solder stop or BSP may be applied using a spin-coating,lamination, or printing process.

Finally, in FIG. 23, solder balls 13′ are applied or adhered toflip-chip substrate 11′, and if not yet separated, the individualpackages may be separated at this point. As discussed above, solderballs 13′ may, for example, be conventional solder balls, semi-balls, orland grid arrays (LGA), and may be adhered, for instance, via solderingthereto.

Additional dies may be configured in accordance with the abovedescription. For example, as shown in FIG. 24, flip-chip wafer-levelpackage 240 may be constructed such that dies 41 and 43 are stackedtogether with die 3′. In this manner, a plurality of dies may beintroduced in such an electronic package. In particular, rather thanadhering a single die to die 3′ via adhesive 15, multiple dies may beadhered thereto.

The present invention may be embodied in other specific forms withoutdeparting from its spirit or essential characteristics. The describedembodiments are to be considered in all respects only as illustrative,not restrictive. The scope of the invention is, therefore, indicated bythe appended claims rather than by the foregoing description. Allchanges that come within the meaning and range of equivalency of theclaims are to be embraced within their scope.

What is claimed is:
 1. A method for manufacturing an electronic package,the method comprising: providing a flip-chip component having a firstdie coupled to a flip-chip substrate; adhering the first die to a seconddie; forming an encapsulation compound around the first die and thesecond die; drilling a set of through encapsulant vias (TEVs) from afirst side of the electronic package to the flip-chip substrate locatedon a second side of the electronic package; filling the set of TEVs withan electrically conductive material; and applying a redistribution layerelectrically connecting a set of contacts on the second die to the setof TEVs on the first side of the electronic package.
 2. The method ofclaim 1 further comprising applying a protection layer covering theredistribution layer and the TEVs.
 3. The method of claim 1 furthercomprising adhering solder balls to the flip-chip substrate.
 4. Themethod of claim 1 further comprising separately testing and burning-inthe flip-chip component.
 5. The method of claim 1 further comprising:adhering the second die to a mold carrier with a releasable adhesive;and removing the mold carrier from the second die.
 6. The method ofclaim 1 further comprising: adhering the flip-chip component to a moldcarrier with a releasable adhesive; and removing the mold carrier fromthe flip-chip component.
 7. The method of claim 6 further comprisingcoupling a set of posts onto the set of contacts on the second die. 8.The method of claim 5 wherein the posts comprise copper.
 9. The methodof claim 6 further comprising: forming the encapsulation compound overthe second die; and exposing the posts.
 10. The method of claim 9wherein exposing the posts comprises grinding the encapsulation compounduntil the posts are exposed, the encapsulation compound forming asubstantially planer surface.
 11. The method of claim 9 wherein exposingthe posts comprises laser drilling the encapsulation compound.